By Bramhananda Marathe,Sandhya Nerale
The function of this booklet is to supply perception and instinct into the analog and analog-mixed sign procedure verification. it's also a trip the writer of this publication has been via with a purpose to take on useful layout and verification demanding situations with kingdom of paintings analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is especially diversified than analog layout and verification. characteristically, the analog block point verification is played by means of the analog designers, and electronic layout verification is played through electronic layout verification engineer. loss of move area ability set makes it tough to accomplish verification at mixed-signal point. consequently, both analog clothier engineer may still research complex electronic verification thoughts or electronic layout verification engineer include analog verification to develop into analog-mixed sign verification engineer. This publication is written preserving this new pattern in brain, for this reason it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification history in brain, the e-book has first five chapters occupied with the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 specializes in the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low energy verification ideas.
Chapter 1: creation to Analog combined sign Verification
This bankruptcy discusses concerning the evolution of the verification methodologies, historical past of analog-mixed sign designs, purposes, and destiny developments.
Chapter 2: Analog layout basics
The goal of this bankruptcy is to offer an summary of the analog layout basics for electronic layout heritage engineers. significant concentration is given on analog habit, layout standards and their thought instead of layout themselves, comparable to voltage/current reference, a few of the uncomplicated key analog layout houses equivalent to achieve, band width, fundamentals of jitter, eye diagram, and so on.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout circulate, combinational and sequential good judgment layout basics, layout for testability, strategies of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy specializes in analog functionality verification and practical verification below the context of combined sign layout hierarchical verification instead of the element functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are developed over the interval which are predicated on predictable caliber and verification potency. The bankruptcy includes the sections at the assurance pushed verification (CDV) technique, statement established verification (ABV) technique, and evaluation of the CDV utilizing Open Verification method (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses concerning the AMS verification stages, selecting the right abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains concerning the purposes of analog behavioral versions, modeling method, easy examples of varied analog behavioral modeling types, choice of accuracy point of the types in line with the verification plan, version verification, and signoff.
Chapter eight: Low energy Verification
The objective of this bankruptcy is to provide an explanation for the low strength layout verification demanding situations, key low energy layout parts, low energy layout innovations, low strength layout and verification cycle, testplanning for low strength layout verification, strength acutely aware electronic, and AMS simulations
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Additional resources for Analog-Mixed Signal Verification
Analog-Mixed Signal Verification by Bramhananda Marathe,Sandhya Nerale